A via is an electrical connection between wiring structures (e.g., wiring layers) in a physical electronic circuit that goes through the plane of one or more adjacent layers. For example, in integrated circuit design, a via is a small opening in an insulating oxide layer that allows a conductive connection between different wiring layers. A via connecting the lowest layer of metal to diffusion or poly is typically called a “contact”.
Fully aligned vias can have challenging integration issues. For example, gapfill of traditional ultra low-k (ULK) materials in the topography is challenging. A reason is that due to the relatively high aspect ratio of topography at advanced technology nodes of 7 nm and beyond, standard ULK materials form voids when deposited and/or cured, which prevents the filling of the topography.
One way to alleviate this gapfill problem is to reduce the recess depth of the fully aligned via structure. However, this cannot be done without minimum insulator concerns. The minimum insulator is a minimum space between two neighboring lines, and pertains primarily to copper (Cu) to Cu separation in the line and via structures. Specifically, the minimum insulator must be above a certain tolerance in order to ensure the electric field between the different conductors does not exceed a certain value. More particularly, the closer the conductors (via structures) come with respect to one another, the greater the likelihood of an instantaneous breakdown of the dielectric occurring.
Another concern with the minimum insulator is the occurrence of time dependent dielectric breakdown (TDDB). In TDDB, the dielectric becomes stressed by the electric field over a period of time, resulting in an eventual break down of the dielectric. In a particular example, Cu ions from the via structure diffuse into the dielectric and eventually form a filament, which creates the dielectric breakdown.
In order to meet minimum insulator requirements, recess depth of the skip via must be maintained at approximately 7 nm or greater. Therefore, reducing the recess depth of the via structure is not feasible. Another approach to address the gapfill issue is to change the material used for the dielectric gap. However, other materials, such as ultra low-k (ULK) materials having a dielectric constant equal to or less than 2.7, may result in voids, or may not have satisfactory electrical properties, amongst other examples.